A typical analog video signal 11 for driving an analog video display is illustrated in FIG. 1. As shown in FIG. 1, the analog video signal 11 is a composite signal having lines of analog data signal 12 combined with other sweep and synchronization (sync) signals, which include a blank level 14, having a front porch 14a and a back porch 14b, and a sync level 16. A blank period 14' is defined as a time period when the analog video signal 11 exhibits the front porch 14a, the sync level 16, and the back porch 14b, and a sync period 16' is defined as the time period in which the analog video signal 11 exhibits the sync level 16. The front porch 14a essentially cues the electron beam associated with a raster display to turn off when the beam sweeps from the end of a scan line to the beginning of the next scan line. The sync level 16 cues the electron beam to change either a scan line or a frame, depending upon its time period, and/or to reset counters and other support circuitry. When the sync level 16 cues a scan line, then it is referred to as a "horizontal sync" (Hsync). When the sync level 16 cues a frame, i.e., when it exhibits an extended time period, then it is referred to as a "vertical sync" (Vsync). Furthermore, the back porch 14b permits initialization of the electron beam and other support circuitry prior to acting upon a new scan line or frame.
If the analog video display is multicolor, then there would generally be one of the analog video signals 11 allocated to each color, such as for red, green, and blue. However, only one of the analog video signals, for instance, the one allocated to green, usually has the sync levels 16.
Recently, there has been a trend in the industry toward developing video displays which are driven by digital pixel data as opposed to analog video signals. An example of such a digital video display is the model LQ12D011TFT LCD flat panel display manufactured and made commercially available by the Sharp Corporation, Japan. Thus, it has recently been desirable to convert the analog video signal 11 of FIG. 1 into digital pixel data for driving a digitally-controlled display. This process can be described graphically with reference to FIG. 1. Referring to FIG. 1, in the process of converting the analog video signal 11 into digital pixel data, the analog data signal 12 is converted to a series of digital codes, depending upon its amplitude at a given point in time. For Sharp's digital display device, the analog data signal 12, which typically represents 256 different intensity levels for a particular color when the analog video signal 11 complies with the RS343A industry standard, must be converted to only 8 intensity levels, as is represented in FIG. 1 by levels 0 through 7. The lowest possible color intensity level is commonly referred to as the "black" level, whereas the highest possible color intensity level is commonly referred to as the "white" level.
In order to convert the analog data signal 12 to digital pixel data, i.e., a series of digital codes, a dot (pixel) clock signal must be generated and synchronized with the original dot clock which created the analog video signal 11. Typically, the dot clock signal is generated with a dot clock generation system 17, as is illustrated in FIG. 2, which employs a phase locked loop (PLL) 19. As shown on FIG. 2, the analog video signal 11 on connection 13 is converted into digital pixel data on connection 15, which is essentially a series of digital codes, or bytes, via an analog-to-digital converter (ADC) 14. Moreover, the ADC 14 is clocked by the dot clock signal on connection 18 from the phase locked loop 19. The phase locked loop 19 comprises an analog video sync separator 21 for generating an analog video sync signal on connection 22 indicative of the presence of sync levels 16 (FIG. 1), a voltage-controlled oscillator (VCO) 23 for generating the dot clock signal on connection 18, a dot clock sync generator 24 for converting the dot clock signal on connection 18 into a dot clock sync signal on connection 25, a phase detector 26 for comparing the phases of the analog video sync signal on connection 22 and the dot clock sync signal on connection 25 and for generating a up and down phase control signals on respective connections 28a, 28b, and a loop filter 27 for receiving the control signals on connections 28a, 28b and for providing a voltage control signal on connection 31 to the VCO 23 in order to increase and decrease the frequency of the dot clock signal on connection 18 output from the VCO 23. In essence, the loop filter 27 converts the control signals on connections 28a, 28b into a voltage amplitude for controlling the VCO 23. Generally, a higher absolute voltage corresponds to a higher absolute frequency. Finally, there is usually an adjustment mechanism associated with the PLL 19, such as with the VCO 23, the phase detector 26, or the loop filter 27, for tuning the PLL 19 so that the dot clock sync signal is matched with the analog video sync signal.
The general operation of the dot clock generation system 17 is as follows. Initially, the VCO 23 is a free running oscillator. The analog video signal 11 is sent to the analog video sync separator 21 which separates out the sync levels 18 from the analog video signal 11 by eliminating any part of the analog video signal 11 above the blank level 14. The resultant analog video sync signal on connection 22 is compared with the dot clock sync signal on connection 25 by the phase detector 26. If the edge (rising or falling) of the analog video sync signal on connection 22 is ahead of the edge of the dot clock sync signal on connection 25, then the phase detector 26 causes the VCO 23 to increase the frequency of the dot clock signal on connection 18 via the up control signal on connection 27a. In the alternative, if the edge of the analog video sync signal on connection 22 is behind the dot clock sync signal on connection 25, then the phase detector 26 will cause the VCO 23 to decrease the frequency of the dot clock signal on connection 18 via the down control signal on connection 27b. Accordingly, the dot clock synch signal on connection 25 will eventually correspond with the analog video sync signal on connection 22, and consequently, the dot clock signal on connection 18 will correspond with the dot clock which created the analog data signal on connection 12 in the analog video signal 11. The dot clock signal on connection 18 can then be used to clock the ADC 14 so that the analog video signal 11 is converted to the digital pixel data 15.
The prior arts dot clock generation systems, as exemplified by the system 17 in FIG. 2, do not provide for accurate generation of the dot clock signal on connection 18. One reason is that the analog video sync separator 21 introduces a certain level of propagation delay to the analog video sync signal on connection 22, which delay is non introduced into the dot clock sync signal on connection 25. Hence, the dot clock sync signal on connection 25 is synchronized by the phase locked loop with an analog video sync signal on connection 22 which does not accurately reflect occurrences of the sync levels 16 within the analog video signal 11. Consequently, the dot clock signal on connection 18 will be skewed slightly from the dot clock which generated the analog data signal 12 within the analog video signal 11.
FIG. 3 graphically illustrates digital-to-analog conversion within the ADC 14 when the dot clock signal on connection 18 is skewed in relationship to the analog data signal 12. The dot clock signal on connection 18 can be skewed in terms of frequency and/or phase (more common). Specifically, as shown in FIG. 3, the analog data 12, which resides between sync and blank levels 14, 16, comprises numerous discrete level regions 29 corresponding to a color value which represents the output from a digital-to-analog converter (DAC) clocked by an original dot clock signal. By way of example the dot clock signal on connection 18 is assumed to be skewed in terms of both frequency and phase with respect to the analog data 12. Because of the skew, the dot clock signal on connection 18 will cause the ADC 14 to sample the analog data 12 at locations 32, which are not necessarily within the level regions 29. This predicament results in inaccurate sampling of color data as well as the elimination of much of the color information. More specifically, as shown in FIG. 3, the sampling at location 1 shows that the digital pixel data 15 will be based upon the amplitude of the analog data 12 situated between level regions 29 as opposed to within a level region 29. Moreover, the level region 34 is effectively skipped by the ADC 14 as a result of the skewed dot clock signal on connection 18.
It should be further noted than conventional systems and 15 processes for converting analog television signals into digital pixel data for memory storage or display are not applicable to the processing of the analog video signal 11 for input to a digitized display. The reason is that the television signals are inherently analog. The ADC's in these conventional systems merely sample the analog television signals at any desired pixel rate and phase. Moreover, pixel sampling errors do not result because the television signals were not originally generated from a dot clock and do not exhibit the level regions 29 (FIG. 3).